From 6bc94b7eb2ecc7c2836c2fc10029542ce92eae11 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 24 Feb 2014 12:41:25 +0100 Subject: Don't blow up constants unneccessarily in Verilog frontend --- frontends/ast/genrtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index bc3783bd..dda069cb 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -906,7 +906,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) detectSignWidth(width_hint, sign_hint); is_signed = sign_hint; - return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint)); + return RTLIL::SigSpec(bitsAsConst()); } // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node -- cgit v1.2.3