From a67cd2d4a284cb945af6d477cc215cef7bdd22a8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 17 Mar 2014 01:56:00 +0100
Subject: Progress in Verific bindings

---
 frontends/verific/verific.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'frontends')

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8b42ca8c..84e5e673 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -429,6 +429,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 		import_attributes(wire->attributes, port);
 		module->add(wire);
 
+		wire->port_id = nl->IndexOf(port) + 1;
+
 		if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
 			wire->port_input = true;
 		if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)
-- 
cgit v1.2.3