From a923a63a892b8f0c39aa740c8fe207462fe2d8c8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 25 Mar 2015 19:46:12 +0100 Subject: Ignore celldefine directive in verilog front-end --- frontends/verilog/verilog_lexer.l | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 3a57514a..8fbaa953 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ +"`celldefine"[^\n]* /* ignore `celldefine */ +"`endcelldefine"[^\n]* /* ignore `endcelldefine */ + "`default_nettype"[ \t]+[^ \t\r\n/]+ { char *p = yytext; while (*p != 0 && *p != ' ' && *p != '\t') p++; -- cgit v1.2.3