From db3c67fd6e140893450a44870ee9a75dd1f48b27 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Wed, 17 Oct 2018 17:59:38 +0200 Subject: New upstream version 0.8 --- frontends/ast/genrtlil.cc | 3 +-- frontends/ast/simplify.cc | 5 +---- frontends/verific/verific.cc | 18 ++---------------- frontends/verilog/verilog_frontend.cc | 23 +---------------------- frontends/verilog/verilog_frontend.h | 9 --------- frontends/verilog/verilog_parser.y | 35 ++++++++--------------------------- 6 files changed, 13 insertions(+), 80 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index c9345ff0..0f7e910f 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -985,8 +985,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) use_const_chunk: if (children.size() != 0) { - if (children[0]->type != AST_RANGE) - log_file_error(filename, linenum, "Single range expected.\n"); + log_assert(children[0]->type == AST_RANGE); int source_width = id2ast->range_left - id2ast->range_right + 1; int source_offset = id2ast->range_right; if (!children[0]->range_valid) { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 71eba547..aa3b982d 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1836,7 +1836,7 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed") + if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell") { if (GetSize(children) != 1) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", @@ -1853,9 +1853,6 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$stable") newNode = new AstNode(AST_EQ, past, present); - else if (str == "\\$changed") - newNode = new AstNode(AST_NE, past, present); - else if (str == "\\$rose") newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index dba3b0f0..c5fa5831 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -118,18 +118,6 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net) return net_map.at(net); } -bool is_blackbox(Netlist *nl) -{ - if (nl->IsBlackBox()) - return true; - - const char *attr = nl->GetAttValue("blackbox"); - if (attr != nullptr && strcmp(attr, "0")) - return true; - - return false; -} - void VerificImporter::import_attributes(dict &attributes, DesignObj *obj) { MapIter mi; @@ -721,7 +709,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se netlist = nl; if (design->has(module_name)) { - if (!nl->IsOperator() && !is_blackbox(nl)) + if (!nl->IsOperator()) log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name()); return; } @@ -730,7 +718,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->name = module_name; design->add(module); - if (is_blackbox(nl)) { + if (nl->IsBlackBox()) { log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); module->set_bool_attribute("\\blackbox"); } else { @@ -1688,7 +1676,6 @@ YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN -#ifdef YOSYS_ENABLE_VERIFIC bool check_noverific_env() { const char *e = getenv("YOSYS_NOVERIFIC"); @@ -1698,7 +1685,6 @@ bool check_noverific_env() return false; return true; } -#endif struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index aeea36a2..8dcc7c5a 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -66,21 +66,12 @@ struct VerilogFrontend : public Frontend { log(" enable support for SystemVerilog assertions and some Yosys extensions\n"); log(" replace the implicit -D SYNTHESIS with -D FORMAL\n"); log("\n"); - log(" -noassert\n"); - log(" ignore assert() statements\n"); - log("\n"); - log(" -noassume\n"); - log(" ignore assume() statements\n"); - log("\n"); log(" -norestrict\n"); - log(" ignore restrict() statements\n"); + log(" ignore restrict() assertions\n"); log("\n"); log(" -assume-asserts\n"); log(" treat all assert() statements like assume() statements\n"); log("\n"); - log(" -assert-assumes\n"); - log(" treat all assume() statements like assert() statements\n"); - log("\n"); log(" -dump_ast1\n"); log(" dump abstract syntax tree (before simplification)\n"); log("\n"); @@ -238,14 +229,6 @@ struct VerilogFrontend : public Frontend { formal_mode = true; continue; } - if (arg == "-noassert") { - noassert_mode = true; - continue; - } - if (arg == "-noassume") { - noassume_mode = true; - continue; - } if (arg == "-norestrict") { norestrict_mode = true; continue; @@ -254,10 +237,6 @@ struct VerilogFrontend : public Frontend { assume_asserts_mode = true; continue; } - if (arg == "-assert-assumes") { - assert_assumes_mode = true; - continue; - } if (arg == "-dump_ast1") { flag_dump_ast1 = true; continue; diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index 523bbc89..16edc798 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -54,21 +54,12 @@ namespace VERILOG_FRONTEND // running in -formal mode extern bool formal_mode; - // running in -noassert mode - extern bool noassert_mode; - - // running in -noassume mode - extern bool noassume_mode; - // running in -norestrict mode extern bool norestrict_mode; // running in -assume-asserts mode extern bool assume_asserts_mode; - // running in -assert-assumes mode - extern bool assert_assumes_mode; - // running in -lib mode extern bool lib_mode; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 16cac146..2389d7d3 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -58,8 +58,7 @@ namespace VERILOG_FRONTEND { bool do_not_require_port_stubs; bool default_nettype_wire; bool sv_mode, formal_mode, lib_mode; - bool noassert_mode, noassume_mode, norestrict_mode; - bool assume_asserts_mode, assert_assumes_mode; + bool norestrict_mode, assume_asserts_mode; bool current_wire_rand, current_wire_const; std::istream *lexin; } @@ -882,15 +881,9 @@ param_decl_list: single_param_decl: TOK_ID '=' expr { - AstNode *node; - if (astbuf1 == nullptr) { - if (!sv_mode) - frontend_verilog_yyerror("syntax error"); - node = new AstNode(AST_PARAMETER); - node->children.push_back(AstNode::mkconst_int(0, true)); - } else { - node = astbuf1->clone(); - } + if (astbuf1 == nullptr) + frontend_verilog_yyerror("syntax error"); + AstNode *node = astbuf1->clone(); node->str = *$1; delete node->children[0]; node->children[0] = $3; @@ -1282,28 +1275,16 @@ opt_stmt_label: assert: opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' { - if (noassert_mode) - delete $5; - else - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5)); + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5)); } | opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' { - if (noassume_mode) - delete $5; - else - ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5)); + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); } | opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' { - if (noassert_mode) - delete $6; - else - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6)); + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6)); } | opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' { - if (noassume_mode) - delete $6; - else - ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6)); + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); } | opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5)); -- cgit v1.2.3