From fe829bdbdc436f425e082ab1cc8c3d276f168945 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 9 Nov 2014 10:44:23 +0100 Subject: Added log_warning() API --- frontends/ast/genrtlil.cc | 12 ++++++------ frontends/ast/simplify.cc | 8 ++++---- frontends/verific/verific.cc | 2 +- frontends/verilog/verilog_lexer.l | 12 ++++++------ 4 files changed, 17 insertions(+), 17 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 68c45179..4a102370 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -869,7 +869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_REALVALUE: { RTLIL::SigSpec sig = realAsConst(width_hint); - log("Warning: converting real value %e to binary %s at %s:%d.\n", + log_warning("converting real value %e to binary %s at %s:%d.\n", realvalue, log_signal(sig), filename.c_str(), linenum); return sig; } @@ -890,7 +890,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; if (flag_autowire) - log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); else log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); } @@ -955,10 +955,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.width == 1) - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", str.c_str(), filename.c_str(), linenum); else - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", str.c_str(), filename.c_str(), linenum, chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); } else { @@ -972,10 +972,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset += add_undef_bits_lsb; } if (add_undef_bits_lsb) - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb); if (add_undef_bits_msb) - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", str.c_str(), filename.c_str(), linenum, add_undef_bits_msb); } } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d8fdb4c5..a78fafbd 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -102,7 +102,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, verbose_activate: if (mem2reg_set.count(mem) == 0) { - log("Warning: Replacing memory %s with list of registers.", mem->str.c_str()); + log_warning("Replacing memory %s with list of registers.", mem->str.c_str()); bool first_element = true; for (auto &place : mem2reg_places[it.first]) { log("%s%s", first_element ? " See " : ", ", place.c_str()); @@ -648,7 +648,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width = children[1]->range_left - children[1]->range_right + 1; if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); - log("Warning: converting real value %e to binary %s at %s:%d.\n", + log_warning("converting real value %e to binary %s at %s:%d.\n", children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); @@ -690,7 +690,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } if (current_scope.count(str) == 0) { - // log("Warning: Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str()); + // log_warning("Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str()); AstNode *auto_wire = new AstNode(AST_AUTOWIRE); auto_wire->str = str; current_ast_mod->children.push_back(auto_wire); @@ -1260,7 +1260,7 @@ skip_dynamic_range_lvalue_expansion:; std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; if (type == AST_ASSIGN_EQ) - log("Warning: Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", + log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", filename.c_str(), linenum); int mem_width, mem_size, addr_bits; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 44dfba0a..79abcf24 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -730,7 +730,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setIsOperator()) - log("Warning: Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name()); + log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name()); } else { if (import_netlist_instance_gates(module, net_map, inst)) continue; diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index ae16ebf7..5e739842 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -254,8 +254,8 @@ supply1 { return TOK_SUPPLY1; } } "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" { - log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"); - log("It is strongly suggested to use `ifdef constructs instead!\n"); + log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n" + "It is strongly suggested to use `ifdef constructs instead!\n"); BEGIN(SYNOPSYS_TRANSLATE_OFF); } . /* ignore synopsys translate_off body */ @@ -266,13 +266,13 @@ supply1 { return TOK_SUPPLY1; } BEGIN(SYNOPSYS_FLAGS); } full_case { - log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"); - log("It is strongly suggested to use verilog x-values and default branches instead!\n"); + log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n" + "It is strongly suggested to use verilog x-values and default branches instead!\n"); return TOK_SYNOPSYS_FULL_CASE; } parallel_case { - log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"); - log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); + log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n" + "It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); return TOK_SYNOPSYS_PARALLEL_CASE; } . /* ignore everything else */ -- cgit v1.2.3