From abf8398216c772bcd23925353f45a17c5d508e8a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 21 Jan 2015 23:59:58 +0000 Subject: Progress in equiv_simple --- kernel/rtlil.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 52293da2..aea99347 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1055,8 +1055,11 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const log_assert(new_mod->refcount_wires_ == 0); log_assert(new_mod->refcount_cells_ == 0); - new_mod->connections_ = connections_; - new_mod->attributes = attributes; + for (auto &conn : connections_) + new_mod->connect(conn); + + for (auto &attr : attributes) + new_mod->attributes[attr.first] = attr.second; for (auto &it : wires_) new_mod->addWire(it.first, it.second); -- cgit v1.2.3