From 0ac915a757a10f50fd74e18365cbcf351885c162 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Mar 2014 11:46:13 +0100 Subject: Progress in Verific bindings --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 420f528a..ee73ebe4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -718,7 +718,7 @@ void RTLIL::Module::check() for (auto &it2 : it.second->parameters) { assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } - if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod") { + if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod" && it.second->type.substr(0, 9) != "$verific$") { InternalCellChecker checker(this, it.second); checker.check(); } -- cgit v1.2.3