From 4724d94fbce587b39cd7343dc8de3b859311f55c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 18:59:05 +0200 Subject: Added $alu cell type --- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 14 ++++++++++++++ 2 files changed, 16 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 515da25c..c1bb1d03 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -108,6 +108,8 @@ struct CellTypes for (auto type : std::vector({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true); + setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true); + setup_type("$assert", {"\\A", "\\EN"}, std::set(), true); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7ba6911a..96b651d8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -557,6 +557,20 @@ namespace { return; } + if (cell->type == "$alu") { + param_bool("\\A_SIGNED"); + param_bool("\\B_SIGNED"); + port("\\A", param("\\A_WIDTH")); + port("\\B", param("\\B_WIDTH")); + port("\\CI", 1); + port("\\BI", 1); + port("\\X", param("\\Y_WIDTH")); + port("\\Y", param("\\Y_WIDTH")); + port("\\CO", param("\\Y_WIDTH")); + check_expected(); + return; + } + if (cell->type == "$logic_not") { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); -- cgit v1.2.3