From da360771a193707b59eac9b95b3bfe1652a057aa Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Sep 2014 22:49:24 +0200
Subject: Create a default selection stack in RTLIL::Design::Design()

---
 kernel/rtlil.cc | 1 +
 kernel/yosys.cc | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f237f57e..35cd54b4 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -228,6 +228,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 RTLIL::Design::Design()
 {
 	refcount_modules_ = 0;
+	selection_stack.push_back(RTLIL::Selection());
 }
 
 RTLIL::Design::~Design()
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 7b8173b6..0ecb4cda 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire)
 void yosys_setup()
 {
 	Pass::init_register();
-
 	yosys_design = new RTLIL::Design;
-	yosys_design->selection_stack.push_back(RTLIL::Selection());
 	log_push();
 }
 
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