From 12603432fed7e0332f09f34fad0bcc9aa88bd456 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 12 Jul 2018 13:41:39 +0200
Subject: Some spelling errors fixed

Gbp-Pq: Name 0009-Some-spelling-errors-fixed.patch
---
 manual/CHAPTER_Overview.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual/CHAPTER_Overview.tex')

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 3009bf2c..4136efed 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties:
 As with modules, the attributes can be Verilog attributes imported by the
 Verilog frontend or attributes assigned by passes.
 
-In Yosys, busses (signal vectors) are represented using a single wire object
+In Yosys, buses (signal vectors) are represented using a single wire object
 with a width > 1. So Yosys does not convert signal vectors to individual signals.
 This makes some aspects of RTLIL more complex but enables Yosys to be used for
 coarse grain synthesis where the cells of the target architecture operate on
-- 
cgit v1.2.3

