From 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 02:32:00 +0200 Subject: Renamed "stdcells.v" to "techmap.v" --- manual/CHAPTER_Techmap.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Techmap.tex') diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex index be74c356..26632d0b 100644 --- a/manual/CHAPTER_Techmap.tex +++ b/manual/CHAPTER_Techmap.tex @@ -27,7 +27,7 @@ cells with the provided implementation. When no map file is provided, {\tt techmap} uses a built-in map file that maps the Yosys RTL cell types to the internal gate library used by Yosys. -The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in +The curious reader may find this map file as {\tt techlibs/common/techmap.v} in the Yosys source tree. Additional features have been added to {\tt techmap} to allow for conditional -- cgit v1.2.3