From 79cbf9067c07ed810b3466174278d77b9a05b46d Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 6 Sep 2014 08:47:06 +0200 Subject: Corrected spelling mistakes found by lintian --- manual/CHAPTER_Techmap.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Techmap.tex') diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex index 26632d0b..e5c7456c 100644 --- a/manual/CHAPTER_Techmap.tex +++ b/manual/CHAPTER_Techmap.tex @@ -32,7 +32,7 @@ the Yosys source tree. Additional features have been added to {\tt techmap} to allow for conditional mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can -for example be usefull if the target architecture supports hardware multipliers for +for example be useful if the target architecture supports hardware multipliers for certain bit-widths but not for others. A usual synthesis flow would first use the {\tt techmap} pass to directly map -- cgit v1.2.3