From 61ed6b32d1f5fbfda9c6effdaa678092f8156bfa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 20 Jul 2013 15:19:12 +0200 Subject: Added Yosys Manual --- manual/FILES_Eval/openmsp430.prj | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 manual/FILES_Eval/openmsp430.prj (limited to 'manual/FILES_Eval/openmsp430.prj') diff --git a/manual/FILES_Eval/openmsp430.prj b/manual/FILES_Eval/openmsp430.prj new file mode 100644 index 00000000..cb8cd271 --- /dev/null +++ b/manual/FILES_Eval/openmsp430.prj @@ -0,0 +1,14 @@ +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v" +verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v" -- cgit v1.2.3