From 98940260e1a0e5d9d5d305b5fabe0aed89c9f57c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 12:46:29 +0100 Subject: Progress in presentation --- manual/PRESENTATION_ExAdv/Makefile | 10 ++++--- manual/PRESENTATION_ExAdv/macc_simple_test.v | 6 +++++ manual/PRESENTATION_ExAdv/macc_simple_test.ys | 36 +++++++++++++++++++++++++ manual/PRESENTATION_ExAdv/macc_simple_test_01.v | 6 +++++ manual/PRESENTATION_ExAdv/macc_simple_test_02.v | 6 +++++ manual/PRESENTATION_ExAdv/macc_simple_xmap.v | 6 +++++ manual/PRESENTATION_ExAdv/select.v | 15 +++++++++++ manual/PRESENTATION_ExAdv/select.ys | 10 +++++++ manual/PRESENTATION_ExAdv/select_01.v | 15 ----------- manual/PRESENTATION_ExAdv/select_01.ys | 10 ------- 10 files changed, 92 insertions(+), 28 deletions(-) create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test.v create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test.ys create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test_01.v create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test_02.v create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_xmap.v create mode 100644 manual/PRESENTATION_ExAdv/select.v create mode 100644 manual/PRESENTATION_ExAdv/select.ys delete mode 100644 manual/PRESENTATION_ExAdv/select_01.v delete mode 100644 manual/PRESENTATION_ExAdv/select_01.ys (limited to 'manual/PRESENTATION_ExAdv') diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile index 2a2858e5..60da3169 100644 --- a/manual/PRESENTATION_ExAdv/Makefile +++ b/manual/PRESENTATION_ExAdv/Makefile @@ -1,8 +1,9 @@ -all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf +all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \ + macc_simple_xmap.pdf -select_01.pdf: select_01.v select_01.ys - ../../yosys select_01.ys +select.pdf: select.v select.ys + ../../yosys select.ys red_or3x1.pdf: red_or3x1_* ../../yosys red_or3x1_test.ys @@ -19,3 +20,6 @@ mulshift.pdf: mulshift_* addshift.pdf: addshift_* ../../yosys addshift_test.ys +macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys + ../../yosys macc_simple_test.ys + diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.v b/manual/PRESENTATION_ExAdv/macc_simple_test.v new file mode 100644 index 00000000..6358a47c --- /dev/null +++ b/manual/PRESENTATION_ExAdv/macc_simple_test.v @@ -0,0 +1,6 @@ +module test(a, b, c, d, y); +input [15:0] a, b; +input [31:0] c, d; +output [31:0] y; +assign y = a * b + c + d; +endmodule diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/manual/PRESENTATION_ExAdv/macc_simple_test.ys new file mode 100644 index 00000000..d5b01237 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/macc_simple_test.ys @@ -0,0 +1,36 @@ +read_verilog macc_simple_test.v +hierarchy -check -top test;; + +show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v + +extract -constports -map macc_simple_xmap.v;; +show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v + +################################################# + +read_verilog macc_simple_test_01.v +hierarchy -check -top test;; + +show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v + +extract -map macc_simple_xmap.v;; +show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v + +################################################# + +design -reset +read_verilog macc_simple_test_02.v +hierarchy -check -top test;; + +show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v + +extract -map macc_simple_xmap.v;; +show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v + +################################################# + +design -reset +read_verilog macc_simple_xmap.v +hierarchy -check -top macc_16_16_32;; + +show -prefix macc_simple_xmap -format pdf -notitle diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_01.v b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v new file mode 100644 index 00000000..8391fb38 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v @@ -0,0 +1,6 @@ +module test(a, b, c, d, x, y); +input [15:0] a, b, c, d; +input [31:0] x; +output [31:0] y; +assign y = a*b + c*d + x; +endmodule diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_02.v b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v new file mode 100644 index 00000000..3630102f --- /dev/null +++ b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v @@ -0,0 +1,6 @@ +module test(a, b, c, d, x, y); +input [15:0] a, b, c, d; +input [31:0] x; +output [31:0] y; +assign y = a*b + (c*d + x); +endmodule diff --git a/manual/PRESENTATION_ExAdv/macc_simple_xmap.v b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v new file mode 100644 index 00000000..42f5bae9 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v @@ -0,0 +1,6 @@ +module macc_16_16_32(a, b, c, y); +input [15:0] a, b; +input [31:0] c; +output [31:0] y; +assign y = a*b + c; +endmodule diff --git a/manual/PRESENTATION_ExAdv/select.v b/manual/PRESENTATION_ExAdv/select.v new file mode 100644 index 00000000..1b0bb7ee --- /dev/null +++ b/manual/PRESENTATION_ExAdv/select.v @@ -0,0 +1,15 @@ +module test(clk, s, a, y); + input clk, s; + input [15:0] a; + output [15:0] y; + reg [15:0] b, c; + + always @(posedge clk) begin + b <= a; + c <= b; + end + + wire [15:0] state_a = (a ^ b) + c; + wire [15:0] state_b = (a ^ b) - c; + assign y = !s ? state_a : state_b; +endmodule diff --git a/manual/PRESENTATION_ExAdv/select.ys b/manual/PRESENTATION_ExAdv/select.ys new file mode 100644 index 00000000..9832c104 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/select.ys @@ -0,0 +1,10 @@ +read_verilog select.v +hierarchy -check -top test +proc; opt +cd test +select -set cone_a state_a %ci*:-$dff +select -set cone_b state_b %ci*:-$dff +select -set cone_ab @cone_a @cone_b %i +show -prefix select -format pdf -notitle \ + -color red @cone_ab -color magenta @cone_a \ + -color blue @cone_b diff --git a/manual/PRESENTATION_ExAdv/select_01.v b/manual/PRESENTATION_ExAdv/select_01.v deleted file mode 100644 index 1b0bb7ee..00000000 --- a/manual/PRESENTATION_ExAdv/select_01.v +++ /dev/null @@ -1,15 +0,0 @@ -module test(clk, s, a, y); - input clk, s; - input [15:0] a; - output [15:0] y; - reg [15:0] b, c; - - always @(posedge clk) begin - b <= a; - c <= b; - end - - wire [15:0] state_a = (a ^ b) + c; - wire [15:0] state_b = (a ^ b) - c; - assign y = !s ? state_a : state_b; -endmodule diff --git a/manual/PRESENTATION_ExAdv/select_01.ys b/manual/PRESENTATION_ExAdv/select_01.ys deleted file mode 100644 index a7fe2728..00000000 --- a/manual/PRESENTATION_ExAdv/select_01.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog select_01.v -hierarchy -check -top test -proc; opt -cd test -select -set cone_a state_a %ci*:-$dff -select -set cone_b state_b %ci*:-$dff -select -set cone_ab @cone_a @cone_b %i -show -prefix select_01 -format pdf -notitle \ - -color red @cone_ab -color magenta @cone_a \ - -color blue @cone_b -- cgit v1.2.3