From f08c71b96c325f2432abb4f95fd823ae243e003b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 17:56:19 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile      |  5 ++++-
 manual/PRESENTATION_ExAdv/mymul_map.v   | 15 +++++++++++++++
 manual/PRESENTATION_ExAdv/mymul_test.v  |  4 ++++
 manual/PRESENTATION_ExAdv/mymul_test.ys | 15 +++++++++++++++
 4 files changed, 38 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_test.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 4ee5886d..74f26327 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -10,3 +10,6 @@ red_or3x1.pdf: red_or3x1_*
 sym_mul.pdf: sym_mul_*
 	../../yosys sym_mul_test.ys
 
+mymul.pdf: mymul_*
+	../../yosys mymul_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mymul_map.v b/manual/PRESENTATION_ExAdv/mymul_map.v
new file mode 100644
index 00000000..e888a7a7
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_map.v
@@ -0,0 +1,15 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+        Y = 0;
+        for (i = 0; i < WIDTH; i=i+1)
+            if (A[i])
+                Y = Y + (B << i);
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.v b/manual/PRESENTATION_ExAdv/mymul_test.v
new file mode 100644
index 00000000..620a06d9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.v
@@ -0,0 +1,4 @@
+module test(A, B, Y);
+    input  [1:0] A, B;
+    output [1:0] Y = A * B;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.ys b/manual/PRESENTATION_ExAdv/mymul_test.ys
new file mode 100644
index 00000000..48203e31
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.ys
@@ -0,0 +1,15 @@
+read_verilog mymul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mymul_map.v;;
+
+rename test test_mapped
+read_verilog mymul_test.v
+miter -equiv test test_mapped miter
+flatten miter
+
+sat -verify -prove trigger 0 miter
+
+splitnets -ports test_mapped/A
+show -prefix mymul -format pdf -notitle test_mapped
-- 
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