From a7aea179599045feafcaf26f5ed334a7318a69b4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Jun 2014 12:50:29 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_Prog/.gitignore    |  1 +
 manual/PRESENTATION_Prog/Makefile      | 18 ++++++++
 manual/PRESENTATION_Prog/absval_ref.v  |  3 ++
 manual/PRESENTATION_Prog/my_cmd.cc     | 78 ++++++++++++++++++++++++++++++++++
 manual/PRESENTATION_Prog/sigmap_test.v |  3 ++
 5 files changed, 103 insertions(+)
 create mode 100644 manual/PRESENTATION_Prog/.gitignore
 create mode 100644 manual/PRESENTATION_Prog/Makefile
 create mode 100644 manual/PRESENTATION_Prog/absval_ref.v
 create mode 100644 manual/PRESENTATION_Prog/my_cmd.cc
 create mode 100644 manual/PRESENTATION_Prog/sigmap_test.v

(limited to 'manual/PRESENTATION_Prog')

diff --git a/manual/PRESENTATION_Prog/.gitignore b/manual/PRESENTATION_Prog/.gitignore
new file mode 100644
index 00000000..7fd56076
--- /dev/null
+++ b/manual/PRESENTATION_Prog/.gitignore
@@ -0,0 +1 @@
+my_cmd.so
diff --git a/manual/PRESENTATION_Prog/Makefile b/manual/PRESENTATION_Prog/Makefile
new file mode 100644
index 00000000..8da6bcd6
--- /dev/null
+++ b/manual/PRESENTATION_Prog/Makefile
@@ -0,0 +1,18 @@
+
+all: test0.log test1.log test2.log
+
+my_cmd.so: my_cmd.cc
+	../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
+
+test0.log: my_cmd.so
+	../../yosys -l test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
+	mv test0.log_new test0.log
+
+test1.log: my_cmd.so
+	../../yosys -l test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
+	mv test1.log_new test1.log
+
+test2.log: my_cmd.so
+	../../yosys -l test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
+	mv test2.log_new test2.log
+
diff --git a/manual/PRESENTATION_Prog/absval_ref.v b/manual/PRESENTATION_Prog/absval_ref.v
new file mode 100644
index 00000000..ca0a115a
--- /dev/null
+++ b/manual/PRESENTATION_Prog/absval_ref.v
@@ -0,0 +1,3 @@
+module absval_ref(input signed [3:0] a, output [3:0] y);
+    assign y = a[3] ? -a : a;
+endmodule
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
new file mode 100644
index 00000000..cf8a4add
--- /dev/null
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -0,0 +1,78 @@
+#include "kernel/rtlil.h"
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include "kernel/sigtools.h"
+
+struct MyPass : public Pass {
+    MyPass() : Pass("my_cmd", "just a simple test") { }
+    virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+    {
+        log("Arguments to my_cmd:\n");
+        for (auto &arg : args)
+            log("  %s\n", arg.c_str());
+
+        log("Modules in current design:\n");
+        for (auto &mod : design->modules)
+            log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
+                    mod.second->wires.size(), mod.second->cells.size());
+    }
+} MyPass;
+
+
+struct Test1Pass : public Pass {
+    Test1Pass() : Pass("test1", "creating the absval module") { }
+    virtual void execute(std::vector<std::string>, RTLIL::Design *design)
+    {
+        RTLIL::Module *module = new RTLIL::Module;
+        module->name = "\\absval";
+
+        RTLIL::Wire *a = module->new_wire(4, "\\a");
+        a->port_input = true;
+        a->port_id = 1;
+
+        RTLIL::Wire *y = module->new_wire(4, "\\y");
+        y->port_output = true;
+        y->port_id = 2;
+
+        RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID);
+        module->addNeg(NEW_ID, a, a_inv, true);
+        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
+
+        log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
+
+        if (design->modules.count(module->name) != 0)
+            log_error("A module with the name %s already exists!\n",
+                    RTLIL::id2cstr(module->name));
+
+        design->modules[module->name] = module;
+    }
+} Test1Pass;
+
+
+struct Test2Pass : public Pass {
+    Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
+    virtual void execute(std::vector<std::string>, RTLIL::Design *design)
+    {
+        if (design->selection_stack.back().empty())
+            log_cmd_error("This command can't operator on an empty selection!\n");
+
+        RTLIL::Module *module = design->modules.at("\\test");
+
+        RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
+                                                   y(module->wires.at("\\y"));
+        log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
+
+        SigMap sigmap(module);
+        log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
+                          sigmap(y) == sigmap(a)); // will print "1 1 1"
+
+        log("Mapped signal x: %s\n", log_signal(sigmap(x)));
+
+        log_header("Doing important stuff!\n");
+        log_push();
+        for (int i = 0; i < 10; i++)
+            log("Log message #%d.\n", i);
+        log_pop();
+    }
+} Test2Pass;
+
diff --git a/manual/PRESENTATION_Prog/sigmap_test.v b/manual/PRESENTATION_Prog/sigmap_test.v
new file mode 100644
index 00000000..18dcf5eb
--- /dev/null
+++ b/manual/PRESENTATION_Prog/sigmap_test.v
@@ -0,0 +1,3 @@
+module test(input a, output x, y);
+assign x = a, y = a;
+endmodule
-- 
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