From b9f2127f5d5a78bab74f511a71b6a369065a0383 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Nov 2014 10:59:48 +0100
Subject: Various documentation updates

---
 manual/PRESENTATION_Prog/my_cmd.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'manual/PRESENTATION_Prog')

diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index 3e3cf13a..1d28ce97 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -1,6 +1,9 @@
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
 struct MyPass : public Pass {
     MyPass() : Pass("my_cmd", "just a simple test") { }
     virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -25,6 +28,7 @@ struct Test1Pass : public Pass {
             log_error("A module with the name absval already exists!\n");
 
         RTLIL::Module *module = design->addModule("\\absval");
+        log("Name of this module: %s\n", log_id(module));
 
         RTLIL::Wire *a = module->addWire("\\a", 4);
         a->port_input = true;
@@ -38,7 +42,7 @@ struct Test1Pass : public Pass {
         module->addNeg(NEW_ID, a, a_inv, true);
         module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
 
-        log("Name of this module: %s\n", log_id(module));
+	module->fixup_ports();
     }
 } Test1Pass;
 
@@ -69,3 +73,4 @@ struct Test2Pass : public Pass {
     }
 } Test2Pass;
 
+PRIVATE_NAMESPACE_END
-- 
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