From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- manual/CHAPTER_Prog/stubnets.cc | 2 +- manual/PRESENTATION_Prog/my_cmd.cc | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'manual') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index a5790743..4d1452c9 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -120,7 +120,7 @@ struct StubnetsPass : public Pass { // call find_stub_nets() for each module that is either // selected as a whole or contains selected objects. - for (auto &it : design->modules) + for (auto &it : design->modules_) if (design->selected_module(it.first)) find_stub_nets(design, it.second, report_bits); } diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc index c724ce37..8dc72c75 100644 --- a/manual/PRESENTATION_Prog/my_cmd.cc +++ b/manual/PRESENTATION_Prog/my_cmd.cc @@ -12,7 +12,7 @@ struct MyPass : public Pass { log(" %s\n", arg.c_str()); log("Modules in current design:\n"); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first), mod.second->wires_.size(), mod.second->cells_.size()); } @@ -40,11 +40,11 @@ struct Test1Pass : public Pass { log("Name of this module: %s\n", RTLIL::id2cstr(module->name)); - if (design->modules.count(module->name) != 0) + if (design->modules_.count(module->name) != 0) log_error("A module with the name %s already exists!\n", RTLIL::id2cstr(module->name)); - design->modules[module->name] = module; + design->modules_[module->name] = module; } } Test1Pass; @@ -56,7 +56,7 @@ struct Test2Pass : public Pass { if (design->selection_stack.back().empty()) log_cmd_error("This command can't operator on an empty selection!\n"); - RTLIL::Module *module = design->modules.at("\\test"); + RTLIL::Module *module = design->modules_.at("\\test"); RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")), y(module->wires_.at("\\y")); -- cgit v1.2.3