From 3d9da919d8ec2f73df77dc1df02b132b12241d8e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 18 Feb 2014 19:37:39 +0100 Subject: Progress in presentation --- manual/PRESENTATION_ExAdv.tex | 37 +++++++++++++++++++++++++++++- manual/PRESENTATION_ExAdv/Makefile | 5 +++- manual/PRESENTATION_ExAdv/addshift_map.v | 20 ++++++++++++++++ manual/PRESENTATION_ExAdv/addshift_test.v | 5 ++++ manual/PRESENTATION_ExAdv/addshift_test.ys | 6 +++++ manual/PRESENTATION_Intro.tex | 2 +- 6 files changed, 72 insertions(+), 3 deletions(-) create mode 100644 manual/PRESENTATION_ExAdv/addshift_map.v create mode 100644 manual/PRESENTATION_ExAdv/addshift_test.v create mode 100644 manual/PRESENTATION_ExAdv/addshift_test.ys (limited to 'manual') diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex index 80210b96..e42a535f 100644 --- a/manual/PRESENTATION_ExAdv.tex +++ b/manual/PRESENTATION_ExAdv.tex @@ -406,7 +406,42 @@ input values to cells. \subsubsection{Handling shorted inputs} \begin{frame}{\subsubsecname} -TBD +\begin{itemize} +\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and +{\tt \_TECHMAP\_CONNMAP\_\it \tt \_} can be used to handle shorted inputs. +\medskip +\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide +number in {\tt \_TECHMAP\_CONNMAP\_\it \tt \_}. +\medskip +\item Each unique signal bit is assigned its own number. Identical fields in the {\tt +\_TECHMAP\_CONNMAP\_\it \tt \_} parameters mean shorted signal bits. +\medskip +\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively. +\medskip +\item Example use-cases: +\begin{itemize} +\item Detecting shared clock or control signals in memory interfaces. +\item In some cases this can be used for for optimization. +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip4.5cm +\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf} +\vss +} +\vskip-0.6cm +\begin{columns} +\column[t]{6cm} +\vskip-0.4cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v} +\column[t]{4.2cm} +\vskip-0.6cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys} +\end{columns} \end{frame} \subsubsection{Notes on using techmap} diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile index 3bbc239a..2a2858e5 100644 --- a/manual/PRESENTATION_ExAdv/Makefile +++ b/manual/PRESENTATION_ExAdv/Makefile @@ -1,5 +1,5 @@ -all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf +all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf select_01.pdf: select_01.v select_01.ys ../../yosys select_01.ys @@ -16,3 +16,6 @@ mymul.pdf: mymul_* mulshift.pdf: mulshift_* ../../yosys mulshift_test.ys +addshift.pdf: addshift_* + ../../yosys addshift_test.ys + diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v new file mode 100644 index 00000000..b6d91b01 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_map.v @@ -0,0 +1,20 @@ +module \$add (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter _TECHMAP_BITS_CONNMAP_ = 0; + parameter _TECHMAP_CONNMAP_A_ = 0; + parameter _TECHMAP_CONNMAP_B_ = 0; + + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH || + _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_; + + assign Y = A << 1; +endmodule diff --git a/manual/PRESENTATION_ExAdv/addshift_test.v b/manual/PRESENTATION_ExAdv/addshift_test.v new file mode 100644 index 00000000..b53271fa --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_test.v @@ -0,0 +1,5 @@ +module test (A, B, X, Y); +input [7:0] A, B; +output [7:0] X = A + B; +output [7:0] Y = A + A; +endmodule diff --git a/manual/PRESENTATION_ExAdv/addshift_test.ys b/manual/PRESENTATION_ExAdv/addshift_test.ys new file mode 100644 index 00000000..c08f1106 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_test.ys @@ -0,0 +1,6 @@ +read_verilog addshift_test.v +hierarchy -check -top test + +techmap -map addshift_map.v;; + +show -prefix addshift -format pdf -notitle diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 27576647..1c07928b 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -359,7 +359,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des Map registers to available hardware flip-flops. }% \only<12>{ - Map logix to available hardware gates. + Map logic to available hardware gates. }% \only<13>{ Clean up the design (just the last step of {\tt opt}). -- cgit v1.2.3