From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 14:11:39 +0200 Subject: Added module->design and cell->module, wire->module pointers --- manual/PRESENTATION_Prog/Makefile | 6 +++--- manual/PRESENTATION_Prog/my_cmd.cc | 35 ++++++++++++++--------------------- 2 files changed, 17 insertions(+), 24 deletions(-) (limited to 'manual') diff --git a/manual/PRESENTATION_Prog/Makefile b/manual/PRESENTATION_Prog/Makefile index 8da6bcd6..794f5c12 100644 --- a/manual/PRESENTATION_Prog/Makefile +++ b/manual/PRESENTATION_Prog/Makefile @@ -5,14 +5,14 @@ my_cmd.so: my_cmd.cc ../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs test0.log: my_cmd.so - ../../yosys -l test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v + ../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v mv test0.log_new test0.log test1.log: my_cmd.so - ../../yosys -l test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v + ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v mv test1.log_new test1.log test2.log: my_cmd.so - ../../yosys -l test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v + ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v mv test2.log_new test2.log diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc index 8dc72c75..381b0587 100644 --- a/manual/PRESENTATION_Prog/my_cmd.cc +++ b/manual/PRESENTATION_Prog/my_cmd.cc @@ -1,6 +1,4 @@ -#include "kernel/rtlil.h" -#include "kernel/register.h" -#include "kernel/log.h" +#include "kernel/yosys.h" #include "kernel/sigtools.h" struct MyPass : public Pass { @@ -12,9 +10,9 @@ struct MyPass : public Pass { log(" %s\n", arg.c_str()); log("Modules in current design:\n"); - for (auto &mod : design->modules_) - log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first), - mod.second->wires_.size(), mod.second->cells_.size()); + for (auto mod : design->modules()) + log(" %s (%zd wires, %zd cells)\n", log_id(mod), + SIZE(mod->wires()), SIZE(mod->cells())); } } MyPass; @@ -23,28 +21,24 @@ struct Test1Pass : public Pass { Test1Pass() : Pass("test1", "creating the absval module") { } virtual void execute(std::vector, RTLIL::Design *design) { - RTLIL::Module *module = new RTLIL::Module; - module->name = "\\absval"; + if (design->has("\\absval") != 0) + log_error("A module with the name absval already exists!\n"); - RTLIL::Wire *a = module->new_wire(4, "\\a"); + RTLIL::Module *module = design->addModule("\\absval"); + + RTLIL::Wire *a = module->addWire("\\a", 4); a->port_input = true; a->port_id = 1; - RTLIL::Wire *y = module->new_wire(4, "\\y"); + RTLIL::Wire *y = module->addWire("\\y", 4); y->port_output = true; y->port_id = 2; - RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID); + RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4); module->addNeg(NEW_ID, a, a_inv, true); - module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y); - - log("Name of this module: %s\n", RTLIL::id2cstr(module->name)); - - if (design->modules_.count(module->name) != 0) - log_error("A module with the name %s already exists!\n", - RTLIL::id2cstr(module->name)); + module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y); - design->modules_[module->name] = module; + log("Name of this module: %s\n", log_id(module)); } } Test1Pass; @@ -58,8 +52,7 @@ struct Test2Pass : public Pass { RTLIL::Module *module = design->modules_.at("\\test"); - RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")), - y(module->wires_.at("\\y")); + RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y")); log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0" SigMap sigmap(module); -- cgit v1.2.3