From f9a307a50b5ce67b67d2b53e8c1334ea23ffd997 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 27 Sep 2014 16:17:53 +0200
Subject: namespace Yosys

---
 passes/cmds/rename.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'passes/cmds/rename.cc')

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 91de364f..1006686e 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -21,6 +21,9 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
 static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
 {
 	from_name = RTLIL::escape_id(from_name);
@@ -196,3 +199,4 @@ struct RenamePass : public Pass {
 	}
 } RenamePass;
  
+PRIVATE_NAMESPACE_END
-- 
cgit v1.2.3


From d92fb5b35eff8c616f1b5de355d13b642e830c8f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Nov 2014 12:38:48 +0100
Subject: Added missing fixup_ports() calls to "rename" command

---
 passes/cmds/rename.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'passes/cmds/rename.cc')

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 1006686e..b2e10e55 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -36,6 +36,8 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 		if (it.first == from_name) {
 			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
 			module->rename(it.second, to_name);
+			if (it.second->port_id)
+				module->fixup_ports();
 			return;
 		}
 
@@ -124,6 +126,7 @@ struct RenamePass : public Pass {
 					new_wires[it.second->name] = it.second;
 				}
 				module->wires_.swap(new_wires);
+				module->fixup_ports();
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
@@ -154,6 +157,7 @@ struct RenamePass : public Pass {
 					new_wires[it.second->name] = it.second;
 				}
 				module->wires_.swap(new_wires);
+				module->fixup_ports();
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
-- 
cgit v1.2.3


From a6c96b986be313368b4fa03eba5cf6987448100c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 26 Dec 2014 10:53:21 +0100
Subject: Added Yosys::{dict,nodict,vector} container types

---
 passes/cmds/rename.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'passes/cmds/rename.cc')

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index b2e10e55..8f24af27 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -118,7 +118,7 @@ struct RenamePass : public Pass {
 				if (!design->selected(module))
 					continue;
 
-				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
 				for (auto &it : module->wires_) {
 					if (it.first[0] == '$' && design->selected(module, it.second))
 						do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@@ -128,7 +128,7 @@ struct RenamePass : public Pass {
 				module->wires_.swap(new_wires);
 				module->fixup_ports();
 
-				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
 					if (it.first[0] == '$' && design->selected(module, it.second))
 						do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@@ -149,7 +149,7 @@ struct RenamePass : public Pass {
 				if (!design->selected(module))
 					continue;
 
-				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
 				for (auto &it : module->wires_) {
 					if (design->selected(module, it.second))
 						if (it.first[0] == '\\' && it.second->port_id == 0)
@@ -159,7 +159,7 @@ struct RenamePass : public Pass {
 				module->wires_.swap(new_wires);
 				module->fixup_ports();
 
-				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells_) {
 					if (design->selected(module, it.second))
 						if (it.first[0] == '\\')
-- 
cgit v1.2.3


From f889e3d38524bb3cb6a10ccd33f788e987c6e14e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 9 Feb 2015 00:18:36 +0100
Subject: Fixed iterator invalidation bug in "rename" command

---
 passes/cmds/rename.cc | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'passes/cmds/rename.cc')

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 8f24af27..17d803e9 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -34,9 +34,10 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 
 	for (auto &it : module->wires_)
 		if (it.first == from_name) {
-			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
-			module->rename(it.second, to_name);
-			if (it.second->port_id)
+			Wire *w = it.second;
+			log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
+			module->rename(w, to_name);
+			if (w->port_id)
 				module->fixup_ports();
 			return;
 		}
-- 
cgit v1.2.3