From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- passes/cmds/splice.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes/cmds/splice.cc') diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 61de4406..691d972c 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -149,7 +149,7 @@ struct SpliceWorker driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) { RTLIL::SigSpec sig = sigmap(it.second); driven_chunks.insert(sig); @@ -175,7 +175,7 @@ struct SpliceWorker SigPool selected_bits; if (!sel_by_cell) - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) selected_bits.add(sigmap(it.second)); @@ -203,7 +203,7 @@ struct SpliceWorker std::vector> rework_wires; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (!no_outputs && it.second->port_output) { if (!design->selected(module, it.second)) continue; -- cgit v1.2.3