From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- passes/fsm/fsm_detect.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/fsm/fsm_detect.cc') diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index e1528f31..a619cf57 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -148,7 +148,7 @@ struct FsmDetectPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; -- cgit v1.2.3