From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:18:00 +0200
Subject: Refactoring: Renamed RTLIL::Design::modules to modules_

---
 passes/fsm/fsm_expand.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/fsm/fsm_expand.cc')

diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 40ec55c1..f107366d 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass {
 		log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			std::vector<RTLIL::Cell*> fsm_cells;
-- 
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