From 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 15:05:18 +0200 Subject: Use only module->addCell() and module->remove() to create and delete cells --- passes/fsm/fsm_extract.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'passes/fsm/fsm_extract.cc') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index dfd025a5..1b5ea1bc 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -270,9 +270,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = new RTLIL::Cell; - fsm_cell->name = stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++); - fsm_cell->type = "$fsm"; + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); fsm_cell->connections["\\CLK"] = clk; fsm_cell->connections["\\ARST"] = arst; fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); @@ -282,7 +280,6 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); - module->cells[fsm_cell->name] = fsm_cell; // rename original state wire -- cgit v1.2.3