From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- passes/fsm/fsm_info.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/fsm/fsm_info.cc') diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index f2d0c1a8..4526939c 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -45,7 +45,7 @@ struct FsmInfoPass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { log("\n"); log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str()); -- cgit v1.2.3