From fefe0fc0430f4f173a25e674708aa0f4f0854b31 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 3 Nov 2016 23:18:00 +0100
Subject: Imported yosys 0.7

---
 passes/fsm/fsm_map.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'passes/fsm/fsm_map.cc')

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 5b32ed59..c4230375 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -272,7 +272,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		}
 		else
 		{
-			RTLIL::SigSpec sig_a, sig_b, sig_s;
+			RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width);
+			RTLIL::SigSpec sig_b, sig_s;
 			int reset_state = fsm_data.reset_state;
 			if (reset_state < 0)
 				reset_state = 0;
-- 
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