From 4569a747f8af3880e23408eb93323afc8088b78b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 10 Oct 2014 16:59:44 +0200 Subject: Renamed SIZE() to GetSize() because of name collision on Win32 --- passes/fsm/fsm_extract.cc | 16 ++++++++-------- passes/fsm/fsm_map.cc | 8 ++++---- passes/fsm/fsm_opt.cc | 6 +++--- passes/fsm/fsm_recode.cc | 2 +- passes/fsm/fsmdata.h | 8 ++++---- 5 files changed, 20 insertions(+), 20 deletions(-) (limited to 'passes/fsm') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index f3369758..e01c5496 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -73,9 +73,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL sig_aa.replace(sig_y, sig_a); RTLIL::SigSpec sig_bb; - for (int i = 0; i < SIZE(sig_b)/SIZE(sig_a); i++) { + for (int i = 0; i < GetSize(sig_b)/GetSize(sig_a); i++) { RTLIL::SigSpec s = sig; - s.replace(sig_y, sig_b.extract(i*SIZE(sig_a), SIZE(sig_a))); + s.replace(sig_y, sig_b.extract(i*GetSize(sig_a), GetSize(sig_a))); sig_bb.append(s); } @@ -98,8 +98,8 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL if (!find_states(sig_aa, dff_out, ctrl, states)) return false; - for (int i = 0; i < SIZE(sig_bb)/SIZE(sig_aa); i++) { - if (!find_states(sig_bb.extract(i*SIZE(sig_aa), SIZE(sig_aa)), dff_out, ctrl, states)) + for (int i = 0; i < GetSize(sig_bb)/GetSize(sig_aa); i++) { + if (!find_states(sig_bb.extract(i*GetSize(sig_aa), GetSize(sig_aa)), dff_out, ctrl, states)) return false; } } @@ -110,7 +110,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec()) { if (dont_care.size() > 0) { - for (int i = 0; i < SIZE(sig); i++) + for (int i = 0; i < GetSize(sig); i++) if (dont_care.extract(sig[i]).size() > 0) sig[i] = noconst_state; } @@ -118,7 +118,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no ce.assign_map.apply(sig); ce.values_map.apply(sig); - for (int i = 0; i < SIZE(sig); i++) + for (int i = 0; i < GetSize(sig); i++) if (sig[i].wire != NULL) sig[i] = noconst_state; @@ -148,7 +148,7 @@ undef_bit_in_next_state: tr.ctrl_out = sig2const(ce, ctrl_out, RTLIL::State::Sx); std::map ctrl_in_bit_indices; - for (int i = 0; i < SIZE(ctrl_in); i++) + for (int i = 0; i < GetSize(ctrl_in); i++) ctrl_in_bit_indices[ctrl_in[i]] = i; for (auto &it : ctrl_in_bit_indices) @@ -290,7 +290,7 @@ static void extract_fsm(RTLIL::Wire *wire) log(" fsm extraction failed: state selection tree is not closed.\n"); return; } - if (SIZE(states) <= 1) { + if (GetSize(states) <= 1) { log(" fsm extraction failed: at least two states are required.\n"); return; } diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 2f6ac854..a260653f 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -30,8 +30,8 @@ PRIVATE_NAMESPACE_BEGIN static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern) { - log_assert(SIZE(super_pattern.bits) == SIZE(sub_pattern.bits)); - for (int i = 0; i < SIZE(super_pattern.bits); i++) + log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits)); + for (int i = 0; i < GetSize(super_pattern.bits); i++) if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) { if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) { if (super_pattern.bits[i] != sub_pattern.bits[i]) @@ -91,7 +91,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnect(next_state_wire, fsm_data.state_table.front()); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 805e3925..6685e8e0 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -43,7 +43,7 @@ struct FsmOpt std::vector new_state_table; std::map old_to_new_state; - for (int i = 0; i < SIZE(fsm_data.state_table); i++) + for (int i = 0; i < GetSize(fsm_data.state_table); i++) if (i != fsm_data.reset_state) unreachable_states.insert(i); @@ -53,12 +53,12 @@ struct FsmOpt if (unreachable_states.empty()) break; - for (int i = 0; i < SIZE(fsm_data.state_table); i++) { + for (int i = 0; i < GetSize(fsm_data.state_table); i++) { if (unreachable_states.count(i)) { log(" Removing unreachable state %s.\n", log_signal(fsm_data.state_table[i])); continue; } - old_to_new_state[i] = SIZE(new_state_table); + old_to_new_state[i] = GetSize(new_state_table); new_state_table.push_back(fsm_data.state_table[i]); } diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 640bed1e..2b9a26d4 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -77,7 +77,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs if (!default_encoding.empty()) encoding = default_encoding; else - encoding = SIZE(fsm_data.state_table) < 32 ? "one-hot" : "binary"; + encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary"; log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str()); } diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 17d22c86..5671d000 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -143,24 +143,24 @@ struct FsmData log("\n"); log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN"); - for (int i = 0; i < SIZE(sig_in); i++) + for (int i = 0; i < GetSize(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT"); - for (int i = 0; i < SIZE(sig_out); i++) + for (int i = 0; i < GetSize(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); log("\n"); log(" State encoding:\n"); - for (int i = 0; i < SIZE(state_table); i++) + for (int i = 0; i < GetSize(state_table); i++) log(" %3d: %10s%s\n", i, log_signal(state_table[i], false), int(i) == reset_state ? " " : ""); log("\n"); log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n"); - for (int i = 0; i < SIZE(transition_table); i++) { + for (int i = 0; i < GetSize(transition_table); i++) { transition_t &tr = transition_table[i]; log(" %5d: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out)); } -- cgit v1.2.3