From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 13:11:01 +0200
Subject: More cleanups related to RTLIL::IdString usage

---
 passes/fsm/fsm_detect.cc  | 2 +-
 passes/fsm/fsm_export.cc  | 2 +-
 passes/fsm/fsm_extract.cc | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'passes/fsm')

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 6025de15..5675dff5 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -26,7 +26,7 @@
 
 static RTLIL::Module *module;
 static SigMap assign_map;
-typedef std::pair<RTLIL::Cell*,std::string> sig2driver_entry_t;
+typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t;
 static SigSet<sig2driver_entry_t> sig2driver, sig2user;
 static std::set<RTLIL::Cell*> muxtree_cells;
 static SigPool sig_at_port;
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index f6f9faa9..97ccf91e 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -62,7 +62,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
 	}
 	else {
 		kiss_name.assign(module->name);
-		kiss_name.append('-' + cell->name + ".kiss2");
+		kiss_name.append('-' + cell->name.str() + ".kiss2");
 	}
 
 	log("\n");
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index cf2075fb..5e71c1f0 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -31,7 +31,7 @@
 
 static RTLIL::Module *module;
 static SigMap assign_map;
-typedef std::pair<std::string, std::string> sig2driver_entry_t;
+typedef std::pair<RTLIL::IdString, RTLIL::IdString> sig2driver_entry_t;
 static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
 
 static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
@@ -277,7 +277,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
 	fsm_cell->setPort("\\CTRL_IN", ctrl_in);
 	fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
-	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
+	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
 	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
 
-- 
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