From f483dce7c231f83937b5944ed0166a70594a0e8b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 29 Apr 2015 07:28:15 +0200 Subject: Added $eq/$neq -> $logic_not/$reduce_bool optimization --- passes/fsm/fsm_extract.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'passes/fsm') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 68667ef0..b5250970 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire) for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_b; + if (cell->hasPort("\\B")) + sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; -- cgit v1.2.3