From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- passes/hierarchy/submod.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/hierarchy') diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d0c9f4b5..2a47002e 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -185,7 +185,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire)); + new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire)); } } -- cgit v1.2.3