From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- passes/memory/memory_dff.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'passes/memory/memory_dff.cc') diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 174417bd..8bae24cf 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, sig); sig.expand(); - for (size_t i = 0; i < sig.__chunks.size(); i++) + for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &chunk = sig.__chunks[i]; + RTLIL::SigChunk &chunk = sig.chunks()[i]; if (chunk.wire == NULL) continue; @@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, q_norm); RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); - if (d.__width != 1) + if (d.size() != 1) continue; - assert(d.__chunks.size() == 1); - chunk = d.__chunks[0]; + assert(d.chunks().size() == 1); + chunk = d.chunks()[0]; clk = cell->connections["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; @@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::Wire *wire = new RTLIL::Wire; wire->name = sstr.str(); - wire->width = sig.__width; + wire->width = sig.size(); module->wires[wire->name] = wire; RTLIL::SigSpec newsig(wire); -- cgit v1.2.3