From 946ddff9cef3ea0b4dad8664319fb13074133775 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 20:12:50 +0200
Subject: Changed a lot of code to the new RTLIL::Wire constructors

---
 passes/memory/memory_dff.cc | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 999c969b..b63b3aec 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -118,18 +118,13 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 	std::stringstream sstr;
 	sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
 
-	RTLIL::Wire *wire = new RTLIL::Wire;
-	wire->name = sstr.str();
-	wire->width = sig.size();
-	module->wires[wire->name] = wire;
-
-	RTLIL::SigSpec newsig(wire);
+	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
 		if (cell->type == "$dff") {
 			RTLIL::SigSpec new_q = cell->get("\\Q");
-			new_q.replace(sig, newsig);
+			new_q.replace(sig, new_sig);
 			cell->set("\\Q", new_q);
 		}
 	}
-- 
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