From ddf3e2dc657da5e441bd9315bf1a86959a07cab9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 31 Oct 2015 22:01:41 +0100 Subject: Bugfix in memory_dff --- passes/memory/memory_dff.cc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'passes/memory/memory_dff.cc') diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 3373369f..2eec0207 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -32,6 +32,7 @@ struct MemoryDffWorker dict invbits; dict sigbit_users_count; dict mux_cells_a, mux_cells_b; + pool forward_merged_dffs, candidate_dffs; MemoryDffWorker(Module *module) : module(module), sigmap(module) { } @@ -46,6 +47,9 @@ struct MemoryDffWorker for (auto cell : dff_cells) { + if (after && forward_merged_dffs.count(cell)) + continue; + SigSpec this_clk = cell->getPort("\\CLK"); bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); @@ -71,6 +75,7 @@ struct MemoryDffWorker bit = d; clk = this_clk; clk_polarity = this_clk_polarity; + candidate_dffs.insert(cell); goto replaced_this_bit; } @@ -87,6 +92,7 @@ struct MemoryDffWorker RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx); bool clk_polarity = 0; + candidate_dffs.clear(); RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) { @@ -106,13 +112,18 @@ struct MemoryDffWorker return; } - if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { + if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) + { + for (auto cell : candidate_dffs) + forward_merged_dffs.insert(cell); + cell->setPort("\\CLK", clk); cell->setPort("\\ADDR", sig_addr); cell->setPort("\\DATA", sig_data); cell->setPort("\\EN", sig_en); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); + log("merged $dff to cell.\n"); return; } -- cgit v1.2.3