From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:18:00 +0200
Subject: Refactoring: Renamed RTLIL::Design::modules to modules_

---
 passes/memory/memory_map.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/memory/memory_map.cc')

diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 4bb0c8cc..53394b19 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -317,7 +317,7 @@ struct MemoryMapPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
 		log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
 		extra_args(args, 1, design);
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				handle_module(design, mod_it.second);
 	}
-- 
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