From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- passes/memory/memory_map.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4f166653..4bb0c8cc 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -295,7 +295,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) if (it.second->type == "$mem" && design->selected(module, it.second)) cells.push_back(it.second); for (auto cell : cells) -- cgit v1.2.3