From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- passes/memory/memory_map.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 32c7e63a..4f166653 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\D", data_reg_in.back()); std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out_name) > 0) + if (module->wires_.count(w_out_name) > 0) w_out_name = genid(cell->name, "", i, "$q"); RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); -- cgit v1.2.3