From 93a70959f3f67ffcee8159b18a5f68904e32a074 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Dec 2013 14:14:05 +0100 Subject: Replaced RTLIL::Const::str with generic decoder method --- passes/memory/memory_collect.cc | 4 ++-- passes/memory/memory_map.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'passes/memory') diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 63cfd677..ca1a3666 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -53,7 +53,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$memwr" && cell->parameters["\\MEMID"].str == memory->name) + if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) { wr_ports++; del_cell_ids.push_back(cell->name); @@ -80,7 +80,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_en.append(en); } - if (cell->type == "$memrd" && cell->parameters["\\MEMID"].str == memory->name) + if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name) { rd_ports++; del_cell_ids.push_back(cell->name); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 1651751a..45c3933c 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -138,7 +138,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\D"] = data_reg_in.back(); RTLIL::Wire *w_out = new RTLIL::Wire; - w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i); + w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); if (module->wires.count(w_out->name) > 0) w_out->name = genid(cell->name, "", i, "$q"); w_out->width = mem_width; -- cgit v1.2.3