From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- passes/memory/memory_collect.cc | 28 +++++------ passes/memory/memory_dff.cc | 38 +++++++-------- passes/memory/memory_map.cc | 74 ++++++++++++++--------------- passes/memory/memory_share.cc | 102 ++++++++++++++++++++-------------------- passes/memory/memory_unpack.cc | 14 +++--- 5 files changed, 128 insertions(+), 128 deletions(-) (limited to 'passes/memory') diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 116b704e..b4242f25 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) wr_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections["\\CLK"]; + RTLIL::SigSpec clk = cell->connections_["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); - RTLIL::SigSpec addr = cell->connections["\\ADDR"]; - RTLIL::SigSpec data = cell->connections["\\DATA"]; - RTLIL::SigSpec en = cell->connections["\\EN"]; + RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; + RTLIL::SigSpec data = cell->connections_["\\DATA"]; + RTLIL::SigSpec en = cell->connections_["\\EN"]; clk.extend(1, false); clk_enable.extend(1, false); @@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) rd_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections["\\CLK"]; + RTLIL::SigSpec clk = cell->connections_["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); - RTLIL::SigSpec addr = cell->connections["\\ADDR"]; - RTLIL::SigSpec data = cell->connections["\\DATA"]; + RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; + RTLIL::SigSpec data = cell->connections_["\\DATA"]; clk.extend(1, false); clk_enable.extend(1, false); @@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->connections["\\WR_CLK"] = sig_wr_clk; - mem->connections["\\WR_ADDR"] = sig_wr_addr; - mem->connections["\\WR_DATA"] = sig_wr_data; - mem->connections["\\WR_EN"] = sig_wr_en; + mem->connections_["\\WR_CLK"] = sig_wr_clk; + mem->connections_["\\WR_ADDR"] = sig_wr_addr; + mem->connections_["\\WR_DATA"] = sig_wr_data; + mem->connections_["\\WR_EN"] = sig_wr_en; assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); @@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); - mem->connections["\\RD_CLK"] = sig_rd_clk; - mem->connections["\\RD_ADDR"] = sig_rd_addr; - mem->connections["\\RD_DATA"] = sig_rd_data; + mem->connections_["\\RD_CLK"] = sig_rd_clk; + mem->connections_["\\RD_ADDR"] = sig_rd_addr; + mem->connections_["\\RD_DATA"] = sig_rd_data; for (auto c : del_cells) module->remove(c); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 56915776..63f7d052 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -25,7 +25,7 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) { - for (auto &conn : module->connections) + for (auto &conn : module->connections_) sig.replace(conn.first, conn.second); } @@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI continue; if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - if (cell->connections["\\CLK"] != clk) + if (cell->connections_["\\CLK"] != clk) continue; if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity) continue; } - RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"]; + RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"]; normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]); if (d.size() != 1) continue; bit = d; - clk = cell->connections["\\CLK"]; + clk = cell->connections_["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; } @@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx); bool clk_polarity = 0; - RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"]; + RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"]; if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } - RTLIL::SigSpec sig_data = cell->connections["\\DATA"]; + RTLIL::SigSpec sig_data = cell->connections_["\\DATA"]; if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } - RTLIL::SigSpec sig_en = cell->connections["\\EN"]; + RTLIL::SigSpec sig_en = cell->connections_["\\EN"]; if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; } if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections["\\CLK"] = clk; - cell->connections["\\ADDR"] = sig_addr; - cell->connections["\\DATA"] = sig_data; - cell->connections["\\EN"] = sig_en; + cell->connections_["\\CLK"] = clk; + cell->connections_["\\ADDR"] = sig_addr; + cell->connections_["\\DATA"] = sig_data; + cell->connections_["\\EN"] = sig_en; cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); @@ -128,7 +128,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff") - cell->connections["\\Q"].replace(sig, newsig); + cell->connections_["\\Q"].replace(sig, newsig); } } @@ -139,13 +139,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) bool clk_polarity = 0; RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_data = cell->connections["\\DATA"]; + RTLIL::SigSpec sig_data = cell->connections_["\\DATA"]; if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(module, sig_data); - cell->connections["\\CLK"] = clk_data; - cell->connections["\\DATA"] = sig_data; + cell->connections_["\\CLK"] = clk_data; + cell->connections_["\\DATA"] = sig_data; cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); @@ -154,12 +154,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"]; + RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"]; if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections["\\CLK"] = clk_addr; - cell->connections["\\ADDR"] = sig_addr; + cell->connections_["\\CLK"] = clk_addr; + cell->connections_["\\ADDR"] = sig_addr; cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b5f0520a..a626b5af 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"]; + RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"]; RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->connections["\\CLK"] = clocks.extract(0, 1); + c->connections_["\\CLK"] = clocks.extract(0, 1); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); + c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); } RTLIL::Wire *w_in = new RTLIL::Wire; @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_in->width = mem_width; module->wires[w_in->name] = w_in; data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->connections["\\D"] = data_reg_in.back(); + c->connections_["\\D"] = data_reg_in.back(); RTLIL::Wire *w_out = new RTLIL::Wire; w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); @@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; module->wires[w_out->name] = w_out; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->connections["\\Q"] = data_reg_out.back(); + c->connections_["\\Q"] = data_reg_out.back(); } } @@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\D"] = rd_addr; + c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); + c->connections_["\\D"] = rd_addr; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w->width = mem_abits; module->wires[w->name] = w; - c->connections["\\Q"] = RTLIL::SigSpec(w); + c->connections_["\\Q"] = RTLIL::SigSpec(w); rd_addr = RTLIL::SigSpec(w); } else @@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\Q"] = rd_signals.back(); + c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); + c->connections_["\\Q"] = rd_signals.back(); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->connections["\\D"] = rd_signals.back(); + c->connections_["\\D"] = rd_signals.back(); } } @@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\Y"] = rd_signals[k]; - c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1); + c->connections_["\\Y"] = rd_signals[k]; + c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1); count_mux++; RTLIL::Wire *w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); w->width = mem_width; module->wires[w->name] = w; - c->connections["\\A"] = RTLIL::SigSpec(w); + c->connections_["\\A"] = RTLIL::SigSpec(w); w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); w->width = mem_width; module->wires[w->name] = w; - c->connections["\\B"] = RTLIL::SigSpec(w); + c->connections_["\\B"] = RTLIL::SigSpec(w); - next_rd_signals.push_back(c->connections["\\A"]); - next_rd_signals.push_back(c->connections["\\B"]); + next_rd_signals.push_back(c->connections_["\\A"]); + next_rd_signals.push_back(c->connections_["\\B"]); } next_rd_signals.swap(rd_signals); } for (int j = 0; j < mem_size; j++) - module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); } log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); @@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits); - c->connections["\\B"] = wr_addr; + c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits); + c->connections_["\\B"] = wr_addr; count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); module->wires[w_seladdr->name] = w_seladdr; - c->connections["\\Y"] = w_seladdr; + c->connections_["\\Y"] = w_seladdr; int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = w; - c->connections["\\B"] = wr_bit; + c->connections_["\\A"] = w; + c->connections_["\\B"] = wr_bit; w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + c->connections_["\\Y"] = RTLIL::SigSpec(w); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->connections["\\A"] = sig.extract(wr_offset, wr_width); - c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); - c->connections["\\S"] = RTLIL::SigSpec(w); + c->connections_["\\A"] = sig.extract(wr_offset, wr_width); + c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width); + c->connections_["\\S"] = RTLIL::SigSpec(w); w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); w->width = wr_width; module->wires[w->name] = w; - c->connections["\\Y"] = w; + c->connections_["\\Y"] = w; sig.replace(wr_offset, w); wr_offset += wr_width; } } - module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig)); + module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig)); } log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 63f6b14f..919e24a4 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -64,16 +64,16 @@ struct MemoryShareWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector sig_a = sigmap(cell->connections.at("\\A")); - std::vector sig_b = sigmap(cell->connections.at("\\B")); - std::vector sig_s = sigmap(cell->connections.at("\\S")); - std::vector sig_y = sigmap(cell->connections.at("\\Y")); + std::vector sig_a = sigmap(cell->connections_.at("\\A")); + std::vector sig_b = sigmap(cell->connections_.at("\\B")); + std::vector sig_s = sigmap(cell->connections_.at("\\S")); + std::vector sig_y = sigmap(cell->connections_.at("\\Y")); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) - cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); return false; } @@ -87,7 +87,7 @@ struct MemoryShareWorker new_state[sig_s[i]] = true; if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) - cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); } std::map new_state = state; @@ -95,7 +95,7 @@ struct MemoryShareWorker new_state[sig_s[i]] = false; if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) - cell->connections.at("\\A").replace(bit_idx, RTLIL::State::Sx); + cell->connections_.at("\\A").replace(bit_idx, RTLIL::State::Sx); return false; } @@ -141,10 +141,10 @@ struct MemoryShareWorker if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_a = sigmap(cell->connections.at("\\A")); - std::vector sig_b = sigmap(cell->connections.at("\\B")); - std::vector sig_s = sigmap(cell->connections.at("\\S")); - std::vector sig_y = sigmap(cell->connections.at("\\Y")); + std::vector sig_a = sigmap(cell->connections_.at("\\A")); + std::vector sig_b = sigmap(cell->connections_.at("\\B")); + std::vector sig_s = sigmap(cell->connections_.at("\\S")); + std::vector sig_y = sigmap(cell->connections_.at("\\Y")); non_feedback_nets.insert(sig_s.begin(), sig_s.end()); @@ -161,7 +161,7 @@ struct MemoryShareWorker cell->parameters.at("\\MEMID").decode_string() == memid) ignore_data_port = true; - for (auto conn : cell_it.second->connections) + for (auto conn : cell_it.second->connections_) { if (ignore_data_port && conn.first == "\\DATA") continue; @@ -191,8 +191,8 @@ struct MemoryShareWorker if (cell->parameters.at("\\CLK_ENABLE").as_bool()) continue; - RTLIL::SigSpec sig_addr = sigmap(cell->connections.at("\\ADDR")); - std::vector sig_data = sigmap(cell->connections.at("\\DATA")); + RTLIL::SigSpec sig_addr = sigmap(cell->connections_.at("\\ADDR")); + std::vector sig_data = sigmap(cell->connections_.at("\\DATA")); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) @@ -212,14 +212,14 @@ struct MemoryShareWorker for (auto cell : wr_ports) { - RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections.at("\\ADDR")); + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections_.at("\\ADDR")); if (!async_rd_bits.count(sig_addr)) continue; log(" Analyzing write port %s.\n", log_id(cell)); - std::vector cell_data = cell->connections.at("\\DATA"); - std::vector cell_en = cell->connections.at("\\EN"); + std::vector cell_data = cell->connections_.at("\\DATA"); + std::vector cell_en = cell->connections_.at("\\EN"); int created_conditions = 0; for (int i = 0; i < int(cell_data.size()); i++) @@ -239,7 +239,7 @@ struct MemoryShareWorker if (created_conditions) { log(" Added enable logic for %d different cases.\n", created_conditions); - cell->connections.at("\\EN") = cell_en; + cell->connections_.at("\\EN") = cell_en; } } } @@ -357,15 +357,15 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) { RTLIL::Cell *cell = wr_ports.at(i); - RTLIL::SigSpec addr = sigmap_xmux(cell->connections.at("\\ADDR")); + RTLIL::SigSpec addr = sigmap_xmux(cell->connections_.at("\\ADDR")); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->connections.at("\\CLK")); + cache_clk = sigmap(cell->connections_.at("\\CLK")); last_port_by_addr.clear(); if (cache_clk_enable) @@ -377,7 +377,7 @@ struct MemoryShareWorker log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); log(" Active bits: "); - std::vector en_bits = sigmap(cell->connections.at("\\EN")); + std::vector en_bits = sigmap(cell->connections_.at("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) { active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; @@ -399,13 +399,13 @@ struct MemoryShareWorker // Force this ports addr input to addr directly (skip don't care muxes) - cell->connections.at("\\ADDR") = addr; + cell->connections_.at("\\ADDR") = addr; // If any of the ports between `last_i' and `i' write to the same address, this // will have priority over whatever `last_i` wrote. So we need to revisit those // ports and mask the EN bits accordingly. - RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections.at("\\EN")); + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections_.at("\\EN")); for (int j = last_i+1; j < i; j++) { @@ -420,20 +420,20 @@ struct MemoryShareWorker found_overlapping_bits_i_j: log(" Creating collosion-detect logic for port %d.\n", j); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); - module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); - merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); + module->addEq(NEW_ID, addr, wr_ports[j]->connections_.at("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections_.at("\\EN"))); } } // Then we need to merge the (masked) EN and the DATA signals. - RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA"); + RTLIL::SigSpec merged_data = wr_ports[last_i]->connections_.at("\\DATA"); if (found_overlapping_bits) { log(" Creating logic for merging DATA and EN ports.\n"); - merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), sigmap(cell->connections.at("\\DATA"))); + merge_en_data(merged_en, merged_data, sigmap(cell->connections_.at("\\EN")), sigmap(cell->connections_.at("\\DATA"))); } else { - RTLIL::SigSpec cell_en = sigmap(cell->connections.at("\\EN")); - RTLIL::SigSpec cell_data = sigmap(cell->connections.at("\\DATA")); + RTLIL::SigSpec cell_en = sigmap(cell->connections_.at("\\EN")); + RTLIL::SigSpec cell_data = sigmap(cell->connections_.at("\\DATA")); for (int k = 0; k < int(en_bits.size()); k++) if (!active_bits_on_port[last_i][k]) { merged_en.replace(k, cell_en.extract(k, 1)); @@ -443,14 +443,14 @@ struct MemoryShareWorker // Connect the new EN and DATA signals and remove the old write port. - cell->connections.at("\\EN") = merged_en; - cell->connections.at("\\DATA") = merged_data; + cell->connections_.at("\\EN") = merged_en; + cell->connections_.at("\\DATA") = merged_data; module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; log(" Active bits: "); - std::vector en_bits = sigmap(cell->connections.at("\\EN")); + std::vector en_bits = sigmap(cell->connections_.at("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) log("%c", active_bits_on_port[i][k] ? '1' : '0'); @@ -489,7 +489,7 @@ struct MemoryShareWorker std::set considered_port_pairs; for (int i = 0; i < int(wr_ports.size()); i++) { - std::vector bits = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + std::vector bits = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); for (auto bit : bits) if (bit == RTLIL::State::S1) goto port_is_always_active; @@ -509,12 +509,12 @@ struct MemoryShareWorker RTLIL::Cell *cell = wr_ports.at(i); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->connections.at("\\CLK")); + cache_clk = sigmap(cell->connections_.at("\\CLK")); } else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) considered_port_pairs.insert(i); @@ -542,7 +542,7 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) { - RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig)); std::vector bits = sig; @@ -585,18 +585,18 @@ struct MemoryShareWorker log(" Merging port %d into port %d.\n", i-1, i); port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); - RTLIL::SigSpec last_addr = wr_ports[i-1]->connections.at("\\ADDR"); - RTLIL::SigSpec last_data = wr_ports[i-1]->connections.at("\\DATA"); - std::vector last_en = modwalker.sigmap(wr_ports[i-1]->connections.at("\\EN")); + RTLIL::SigSpec last_addr = wr_ports[i-1]->connections_.at("\\ADDR"); + RTLIL::SigSpec last_data = wr_ports[i-1]->connections_.at("\\DATA"); + std::vector last_en = modwalker.sigmap(wr_ports[i-1]->connections_.at("\\EN")); - RTLIL::SigSpec this_addr = wr_ports[i]->connections.at("\\ADDR"); - RTLIL::SigSpec this_data = wr_ports[i]->connections.at("\\DATA"); - std::vector this_en = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + RTLIL::SigSpec this_addr = wr_ports[i]->connections_.at("\\ADDR"); + RTLIL::SigSpec this_data = wr_ports[i]->connections_.at("\\DATA"); + std::vector this_en = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); - wr_ports[i]->connections.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); - wr_ports[i]->connections.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); + wr_ports[i]->connections_.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); + wr_ports[i]->connections_.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -614,7 +614,7 @@ struct MemoryShareWorker } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); - wr_ports[i]->connections.at("\\EN") = en; + wr_ports[i]->connections_.at("\\EN") = en; module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; @@ -653,18 +653,18 @@ struct MemoryShareWorker if (cell->type == "$mux") { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections.at("\\A")); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections.at("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections_.at("\\A")); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections_.at("\\B")); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->connections.at("\\Y"), sig_b); + sigmap_xmux.add(cell->connections_.at("\\Y"), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->connections.at("\\Y"), sig_a); + sigmap_xmux.add(cell->connections_.at("\\Y"), sig_a); } if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_y = sigmap(cell->connections.at("\\Y")); + std::vector sig_y = sigmap(cell->connections_.at("\\Y")); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair(cell, i); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 97cda144..9c457ad5 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1); - cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits); - cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width); + cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1); + cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits); + cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width); } for (int i = 0; i < num_wr_ports; i++) @@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; - cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1); - cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width); - cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits); - cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width); + cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1); + cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width); + cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits); + cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width); } module->remove(memory); -- cgit v1.2.3