From d2ff5d9994f83125578902587bdebd5b749c1beb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 Jul 2015 13:28:00 +0200 Subject: Do not collect disabled $memwr cells --- passes/memory/memory_collect.cc | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) (limited to 'passes/memory') diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6bc4b44c..134b5e8e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -110,21 +110,24 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec en = sigmap(cell->getPort("\\EN")); - clk.extend_u0(1, false); - clk_enable.extend_u0(1, false); - clk_polarity.extend_u0(1, false); - addr.extend_u0(addr_bits, false); - data.extend_u0(memory->width, false); - en.extend_u0(memory->width, false); - - sig_wr_clk.append(clk); - sig_wr_clk_enable.append(clk_enable); - sig_wr_clk_polarity.append(clk_polarity); - sig_wr_addr.append(addr); - sig_wr_data.append(data); - sig_wr_en.append(en); - - wr_ports++; + if (!en.is_fully_zero()) + { + clk.extend_u0(1, false); + clk_enable.extend_u0(1, false); + clk_polarity.extend_u0(1, false); + addr.extend_u0(addr_bits, false); + data.extend_u0(memory->width, false); + en.extend_u0(memory->width, false); + + sig_wr_clk.append(clk); + sig_wr_clk_enable.append(clk_enable); + sig_wr_clk_polarity.append(clk_polarity); + sig_wr_addr.append(addr); + sig_wr_data.append(data); + sig_wr_en.append(en); + + wr_ports++; + } continue; } -- cgit v1.2.3