From 0c86d6106c3ff4cd7628b1206281eb6080f8bf51 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 15:38:02 +0200 Subject: Added SigPool::check(bit) --- passes/opt/opt_clean.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/opt/opt_clean.cc') diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 76a905b2..6c20bddb 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -251,10 +251,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (int i = 0; i < SIZE(sig); i++) { if (sig[i].wire == NULL) continue; - if (!used_signals_nodrivers.check_any(sig[i])) { + if (!used_signals_nodrivers.check(sig[i])) { if (!unused_bits.empty()) unused_bits += " "; - unused_bits += stringf("%zd", i); + unused_bits += stringf("%d", i); } } if (unused_bits.empty() || wire->port_id != 0) -- cgit v1.2.3