From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- passes/proc/proc_init.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/proc/proc_init.cc') diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 5976c216..3607905f 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -101,7 +101,7 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) -- cgit v1.2.3