From 5033b51947a6ef02cb785b5622e993335efa750a Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 30 Aug 2018 20:46:20 +0200 Subject: New upstream version 0.7+20180830git0b7a184 --- passes/proc/proc.cc | 4 ++-- passes/proc/proc_arst.cc | 4 ++-- passes/proc/proc_clean.cc | 4 ++-- passes/proc/proc_dff.cc | 9 +++++---- passes/proc/proc_dlatch.cc | 20 +++++++++++--------- passes/proc/proc_init.cc | 4 ++-- passes/proc/proc_mux.cc | 4 ++-- passes/proc/proc_rmdead.cc | 4 ++-- 8 files changed, 28 insertions(+), 25 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index d5366f26..ef7cb0f7 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ProcPass : public Pass { ProcPass() : Pass("proc", "translate processes to netlists") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -57,7 +57,7 @@ struct ProcPass : public Pass { log(" executed in -ifx mode.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string global_arst; bool ifxmode = false; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 216b00dd..b69eba3f 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -203,7 +203,7 @@ restart_proc_arst: struct ProcArstPass : public Pass { ProcArstPass() : Pass("proc_arst", "detect asynchronous resets") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -221,7 +221,7 @@ struct ProcArstPass : public Pass { log(" in the 'init' attribute on the net.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string global_arst; bool global_arst_neg = false; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 7dbabc21..b9e43d1d 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -143,7 +143,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count) struct ProcCleanPass : public Pass { ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -153,7 +153,7 @@ struct ProcCleanPass : public Pass { log("if it contains only empty structures.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { int total_count = 0; log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n"); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 98653dc6..519d35cd 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -322,6 +322,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } } + SigSpec sig_q = sig; ce.assign_map.apply(insig); ce.assign_map.apply(rstval); ce.assign_map.apply(sig); @@ -350,13 +351,13 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) else if (!rstval.is_fully_const() && !ce.eval(rstval)) { log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval)); - gen_dffsr(mod, insig, rstval, sig, + gen_dffsr(mod, insig, rstval, sig_q, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.as_const(), sig, + gen_dff(mod, insig, rstval.as_const(), sig_q, sync_edge && sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge ? sync_edge->signal : SigSpec(), @@ -369,7 +370,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) struct ProcDffPass : public Pass { ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -379,7 +380,7 @@ struct ProcDffPass : public Pass { log("d-type flip-flop cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 6621afd3..d9d5dfbe 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -217,7 +217,7 @@ struct proc_dlatch_db_t return make_inner(children); } - SigBit make_hold(int n) + SigBit make_hold(int n, string &src) { if (n == true_node) return State::S1; @@ -235,20 +235,20 @@ struct proc_dlatch_db_t if (rule.match == State::S1) and_bits.append(rule.signal); else if (rule.match == State::S0) - and_bits.append(module->Not(NEW_ID, rule.signal)); + and_bits.append(module->Not(NEW_ID, rule.signal, false, src)); else - and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match)); + and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match, false, src)); } if (!rule.children.empty()) { SigSpec or_bits; for (int k : rule.children) - or_bits.append(make_hold(k)); - and_bits.append(module->ReduceOr(NEW_ID, or_bits)); + or_bits.append(make_hold(k, src)); + and_bits.append(module->ReduceOr(NEW_ID, or_bits, false, src)); } if (GetSize(and_bits) == 2) - and_bits = module->And(NEW_ID, and_bits[0], and_bits[1]); + and_bits = module->And(NEW_ID, and_bits[0], and_bits[1], false, src); log_assert(GetSize(and_bits) == 1); rules_sig[n] = and_bits[0]; @@ -340,6 +340,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) RTLIL::SigSig latches_bits, nolatches_bits; dict latches_out_in; dict latches_hold; + std::string src = proc->get_src_attribute(); for (auto sr : proc->syncs) { @@ -405,7 +406,8 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) SigSpec lhs = latches_bits.first.extract(offset, width); SigSpec rhs = latches_bits.second.extract(offset, width); - Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n)), rhs, lhs); + Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs); + cell->set_src_attribute(src); db.generated_dlatches.insert(cell); log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", @@ -420,7 +422,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) struct ProcDlatchPass : public Pass { ProcDlatchPass() : Pass("proc_dlatch", "extract latches from processes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -430,7 +432,7 @@ struct ProcDlatchPass : public Pass { log("d-type latches.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n"); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 0c8fb83d..e2dc07e5 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -102,7 +102,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) struct ProcInitPass : public Pass { ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -113,7 +113,7 @@ struct ProcInitPass : public Pass { log("respective wire.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_INIT pass (extract init attributes).\n"); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 57e131ca..1329c1fe 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -382,7 +382,7 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode) struct ProcMuxPass : public Pass { ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -396,7 +396,7 @@ struct ProcMuxPass : public Pass { log(" 'case' expressions and 'if' conditions.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool ifxmode = false; log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n"); diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 5672fb47..7c334e66 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -65,7 +65,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) struct ProcRmdeadPass : public Pass { ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -74,7 +74,7 @@ struct ProcRmdeadPass : public Pass { log("This pass identifies unreachable branches in decision trees and removes them.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n"); -- cgit v1.2.3