From 1434312fdd1290ac21eb57c79c1999e775cdba54 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Jun 2013 14:11:50 +0200
Subject: Various improvements in sat_solve pass and SAT generator

---
 passes/sat/example.ys | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'passes/sat/example.ys')

diff --git a/passes/sat/example.ys b/passes/sat/example.ys
index b6d131c9..d4037f78 100644
--- a/passes/sat/example.ys
+++ b/passes/sat/example.ys
@@ -1,3 +1,5 @@
 read_verilog example.v
-techmap; opt; abc; opt
-sat_solve -set y 1'b1
+proc; opt_clean
+sat_solve -set y 1'b1 example001
+sat_solve -set y 1'b1 example002
+sat_solve -set y 1'b1 example003
-- 
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