From 23a79730945f2a0e2cc61a2d6a37281dff4be81d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 8 Jun 2013 15:12:08 +0200 Subject: Added support for shifter cells to SAT generator --- passes/sat/example.ys | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'passes/sat/example.ys') diff --git a/passes/sat/example.ys b/passes/sat/example.ys index d4037f78..3de8c799 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -2,4 +2,5 @@ read_verilog example.v proc; opt_clean sat_solve -set y 1'b1 example001 sat_solve -set y 1'b1 example002 -sat_solve -set y 1'b1 example003 +sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 +sat_solve -set y 1'b1 example004 -- cgit v1.2.3