From a75b249427923c7f3ea604c5748291bdba25d1d0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 9 Jun 2013 18:07:05 +0200 Subject: Implemented temporal induction proofs in sat_solve --- passes/sat/example.ys | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'passes/sat/example.ys') diff --git a/passes/sat/example.ys b/passes/sat/example.ys index 19f8f50e..c532c1fb 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,11 +1,13 @@ + read_verilog example.v proc; opt_clean + sat_solve -set y 1'b1 example001 sat_solve -set y 1'b1 example002 sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 sat_solve -set y 1'b1 example004 sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 -sat_solve -prove y 1'b0 example001 -# sat_solve -show rst,counter -prove y 1'b0 -set-at 1 rst 1'b1 -seq 1 example004 +sat_solve -prove y 1'b0 -show rst,counter,y example004 +sat_solve -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 -- cgit v1.2.3