From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- passes/sat/share.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/sat/share.cc') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 0ee5af18..facacf19 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -61,7 +61,7 @@ struct ShareWorker queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (!fwd_ct.cell_known(it.second->type)) { std::set &bits = modwalker.cell_inputs[it.second]; queue_bits.insert(bits.begin(), bits.end()); @@ -101,7 +101,7 @@ struct ShareWorker void find_shareable_cells() { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; -- cgit v1.2.3