From 260c19ec5a3adb292158658dd69a352b9325ab64 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:00:16 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 --- passes/sat/share.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes/sat') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 738b0bd6..724bc3f9 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.size()); - RTLIL::SigSpec new_y2(y, y2.size()); + RTLIL::SigSpec new_y1(y, y1.size(), 0); + RTLIL::SigSpec new_y2(y, y2.size(), 0); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.size()); - RTLIL::SigSpec new_y2(y, y2.size()); + RTLIL::SigSpec new_y1(y, y1.size(), 0); + RTLIL::SigSpec new_y2(y, y2.size(), 0); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); -- cgit v1.2.3 From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:40:31 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 --- passes/sat/eval.cc | 4 ++-- passes/sat/miter.cc | 2 +- passes/sat/share.cc | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'passes/sat') diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 73235e93..91b42812 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -260,8 +260,8 @@ struct VlogHammerReporter for (int i = 0; i < int(inputs.size()); i++) { RTLIL::Wire *wire = module->wires.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { - ce.set(RTLIL::SigSpec(wire, 1, j), bits.back()); - recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j)); + ce.set(RTLIL::SigSpec::grml(wire, j), bits.back()); + recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j)); recorded_set_vals.bits.push_back(bits.back()); bits.pop_back(); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 79857c5e..51cf3ae0 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i); + eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i); eqx_cell->connections["\\B"] = RTLIL::State::Sx; eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); miter_module->add(eqx_cell); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 724bc3f9..c209e8ed 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.size(), 0); - RTLIL::SigSpec new_y2(y, y2.size(), 0); + RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); + RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.size(), 0); - RTLIL::SigSpec new_y2(y, y2.size(), 0); + RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); + RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -620,7 +620,7 @@ struct ShareWorker RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1)); } if (all_cases_wire->width == 1) return all_cases_wire; -- cgit v1.2.3 From ec923652e2eb721aa16657e54a67666f855c3d65 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:48:26 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 --- passes/sat/eval.cc | 4 ++-- passes/sat/miter.cc | 2 +- passes/sat/share.cc | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'passes/sat') diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 91b42812..902dedb6 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -260,8 +260,8 @@ struct VlogHammerReporter for (int i = 0; i < int(inputs.size()); i++) { RTLIL::Wire *wire = module->wires.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { - ce.set(RTLIL::SigSpec::grml(wire, j), bits.back()); - recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j)); + ce.set(RTLIL::SigSpec(wire, j), bits.back()); + recorded_set_vars.append(RTLIL::SigSpec(wire, j)); recorded_set_vals.bits.push_back(bits.back()); bits.pop_back(); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 51cf3ae0..12384e2c 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i); + eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i); eqx_cell->connections["\\B"] = RTLIL::State::Sx; eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); miter_module->add(eqx_cell); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index c209e8ed..ede2fa88 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); - RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); + RTLIL::SigSpec new_y1(y, 0, y1.size()); + RTLIL::SigSpec new_y2(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); - RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); + RTLIL::SigSpec new_y1(y, 0, y1.size()); + RTLIL::SigSpec new_y2(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -620,7 +620,7 @@ struct ShareWorker RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1)); + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)); } if (all_cases_wire->width == 1) return all_cases_wire; -- cgit v1.2.3