From f092b5014895dc5dc62b8103fcedf94cfa9f85a8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Aug 2014 14:11:40 +0200
Subject: Renamed $_INV_ cell type to $_NOT_

---
 passes/sat/freduce.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 7b9fb207..bfed0005 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -623,7 +623,7 @@ struct FreduceWorker
 				batches.push_back(outputs);
 				bits_full_total += outputs.size();
 			}
-			if (inv_mode && it.second->type == "$_INV_")
+			if (inv_mode && it.second->type == "$_NOT_")
 				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
 		}
 
@@ -718,7 +718,7 @@ struct FreduceWorker
 					{
 						inv_sig = module->addWire(NEW_ID);
 
-						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
+						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
 						inv_cell->setPort("\\A", grp[0].bit);
 						inv_cell->setPort("\\Y", inv_sig);
 					}
-- 
cgit v1.2.3