From f9a307a50b5ce67b67d2b53e8c1334ea23ffd997 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 27 Sep 2014 16:17:53 +0200 Subject: namespace Yosys --- passes/sat/eval.cc | 6 +++--- passes/sat/expose.cc | 18 +++++++++++------- passes/sat/freduce.cc | 6 +++--- passes/sat/miter.cc | 6 +++++- passes/sat/sat.cc | 12 ++++++------ 5 files changed, 28 insertions(+), 20 deletions(-) (limited to 'passes/sat') diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index f07ad943..e58a194e 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -31,7 +31,8 @@ #include #include -namespace { +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN /* this should only be used for regression testing of ConstEval -- see vloghammer */ struct BruteForceEquivChecker @@ -357,8 +358,6 @@ struct VlogHammerReporter } }; -} /* namespace */ - struct EvalPass : public Pass { EvalPass() : Pass("eval", "evaluate the circuit given an input") { } virtual void help() @@ -601,3 +600,4 @@ struct EvalPass : public Pass { } } EvalPass; +PRIVATE_NAMESPACE_END diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index e856fdf7..46ebdb84 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -23,6 +23,9 @@ #include "kernel/rtlil.h" #include "kernel/log.h" +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + struct dff_map_info_t { RTLIL::SigSpec sig_d, sig_clk, sig_arst; bool clk_polarity, arst_polarity; @@ -37,7 +40,7 @@ struct dff_map_bit_info_t { RTLIL::Cell *cell; }; -static bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) +bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) { if (wire->name[0] == '$' || dff_dq_map.count(wire->name)) return false; @@ -46,7 +49,7 @@ static bool consider_wire(RTLIL::Wire *wire, std::map &dff_cells, RTLIL::Cell *cell) +bool consider_cell(RTLIL::Design *design, std::set &dff_cells, RTLIL::Cell *cell) { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; @@ -55,7 +58,7 @@ static bool consider_cell(RTLIL::Design *design, std::set &dff_ return true; } -static bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2) +bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2) { log_assert(wire1->name == wire2->name); if (wire1->width != wire2->width) @@ -63,7 +66,7 @@ static bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2) return true; } -static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2) +bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2) { log_assert(cell1->name == cell2->name); if (cell1->type != cell2->type) @@ -73,7 +76,7 @@ static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2) return true; } -static void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) +void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) { CellTypes ct; ct.setup_internals_mem(); @@ -93,7 +96,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module * } } -static void create_dff_dq_map(std::map &map, RTLIL::Design *design, RTLIL::Module *module) +void create_dff_dq_map(std::map &map, RTLIL::Design *design, RTLIL::Module *module) { std::map bit_info; SigMap sigmap(module); @@ -208,7 +211,7 @@ static void create_dff_dq_map(std::map &map, RT } } -static RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1) +RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1) { if (module->count_id(name)) log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name)); @@ -644,3 +647,4 @@ struct ExposePass : public Pass { } } ExposePass; +PRIVATE_NAMESPACE_END diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index bfed0005..fbca3586 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -28,7 +28,8 @@ #include #include -namespace { +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN bool inv_mode; int verbose_level, reduce_counter, reduce_stop_at; @@ -745,8 +746,6 @@ struct FreduceWorker } }; -} /* namespace */ - struct FreducePass : public Pass { FreducePass() : Pass("freduce", "perform functional reduction") { } virtual void help() @@ -827,3 +826,4 @@ struct FreducePass : public Pass { } } FreducePass; +PRIVATE_NAMESPACE_END diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index b3adefb9..9853cd0c 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -21,7 +21,10 @@ #include "kernel/rtlil.h" #include "kernel/log.h" -static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Design *design) +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Design *design) { bool flag_ignore_gold_x = false; bool flag_make_outputs = false; @@ -299,3 +302,4 @@ struct MiterPass : public Pass { } } MiterPass; +PRIVATE_NAMESPACE_END diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index fd0abf4a..f0c88e52 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -33,7 +33,8 @@ #include #include -namespace { +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN struct SatHelper { @@ -766,9 +767,7 @@ struct SatHelper } }; -} /* namespace */ - -static void print_proof_failed() +void print_proof_failed() { log("\n"); log(" ______ ___ ___ _ _ _ _ \n"); @@ -780,7 +779,7 @@ static void print_proof_failed() log("\n"); } -static void print_timeout() +void print_timeout() { log("\n"); log(" _____ _ _ _____ ____ _ _____\n"); @@ -791,7 +790,7 @@ static void print_timeout() log("\n"); } -static void print_qed() +void print_qed() { log("\n"); log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n"); @@ -1484,3 +1483,4 @@ struct SatPass : public Pass { } } SatPass; +PRIVATE_NAMESPACE_END -- cgit v1.2.3